1. Field of the Invention
The present invention relates to CMOS memory cells having PMOS and NMOS transistors with a common floating gate configured so that program and erase occurs through the gate oxide of the NMOS and PMOS transistors. More particularly, the present invention relates to circuitry and a method for utilizing the circuitry to reduce leakage current from the CMOS memory cell, and to enable the cell to be used in Programmable Array Logic (PAL) devices.
2. Description of the Related Art
FIG. 1 shows a circuit configuration of a CMOS memory cell 100 having a PMOS transistor 102 and an NMOS transistor 104 enabling utilization of tunneling through the NMOS and PMOS transistors during program and erase. The PMOS transistor 102 and NMOS transistor 104 have a common floating gate. The drains of transistors 102 and 104 connect together to form an output of the CMOS cell. A capacitor 106 is connected to couple bias voltage from an array control gate (ACG) node to the common floating gate. Bias voltage is provided to the source of the NMOS transistor 104 through a chip ground or Vss pin. A PMOS pass gate transistor 108 supplies a word control (WC) voltage to the source of PMOS transistor 102 as controlled by a word line (WL) voltage supplied to its gate. Transistor 108 is a PMOS device to avoid having to increase the WC voltage above the threshold of an NMOS device during programming. The CMOS memory cell 100 is described in detail, along with methods for its program and erase, in the cross-referenced application referred to above, and incorporated herein by reference.
FIG. 2 shows a layout for the cell of FIG. 1. The layout for the CMOS cell 100 is formed in a p type substrate. Capacitor 106 is formed using an n+ type implant region 110, including a programming junction region, formed in the p type substrate. Capacitor 106 also includes a gate oxide layer and a common floating gate (F.G.) 112 overlying the n+ implant region 110. Transistor 104 is formed using n+ implant regions 114 and 116 in the p type substrate with the gate oxide region and common floating gate 112 bridging the n+ implant regions 114 and 116. Transistor 102 is formed using p type regions 118 and 120 included in an n+ type well 122, which is included in the p type substrate. Transistor 102 also includes the gate oxide region and common floating gate 112 bridging the two p type regions 118 and 120. Transistor 108 is formed using a polysilicon (POLY) word line (WL) region 124 on the substrate bridging the p type implant regions 120 of transistor 102 with an additional p type implant region 126.
As indicated in the cross-referenced patent, the layout of FIG. 2 might be modified to include a double polysilicon layer to enable components of capacitor 106 to be stacked above the gate oxide layer and polysilicon floating gate 112 of transistors 102 and 104 to reduce required space on an integrated circuit for the CMOS cell of FIG. 1.
To program the CMOS memory cell 100, a voltage is applied between the array control gate (ACG) node of capacitor 106 and the source of the PMOS transistor 102 so that electrons transfer from the common floating gate to the source of the PMOS transistor 102. A high impedance is applied to the source of the NMOS transistor 104 during programming to prevent depletion of its channel which would occur if an NMOS transistor 104 were biased to remove electrons from the common floating gate.
To erase the CMOS memory cell 100, a voltage is applied between the array control gate (ACG) node of capacitor 106 and the source of the NMOS transistor 104 so that electrons transfer from the source of the NMOS transistor 104 to the common floating gate. A high impedance is further applied to the source of the PMOS transistor 102 during erase to prevent depletion of its channel which would occur if a PMOS transistor 102 were biased to add electrons to the floating gate.
Suggested voltages to apply to the CMOS memory cell 100 of FIG. 1 during program, erase and read are listed in Table I below.
TABLE I ______________________________________ WC WL ACG Vss ______________________________________ Program 12 5 0 Hiz Erase Hiz 0 12 0 Read 5 0 2.5 0 ______________________________________
As indicated in the cross-referenced patent, during read alternative voltages might be applied to CMOS cell 100. For instance, the CMOS cell can be utilized in a low power device, which during read will utilize a WC voltage of 3 V and an ACG voltage of 1/2 the WC voltage, or 1.5V.
To assure charge storage on the floating gate of the CMOS memory cell 100 is practical to turn on one of transistors 102 and 104 while turning the other off during read, Vcc may be applied through a voltage reference as WC to the source of the PMOS transistor 102. With Vcc applied directly from an external source to a chip Vcc pin, unregulated variations in Vcc occur. Such variations in Vcc require that an unacceptably high voltage be applied to the common floating gate to assure PMOS transistor 102 can be turned off. U.S. patent application Ser. No. 08/426,741, entitled "Reference for CMOS Memory Cell Having PMOS and NMOS Transistors With a Common Floating Gate" filed Apr. 21, 1994, (hereinafter, the CMOS reference patent application), incorporated herein by reference, discloses such a reference for a CMOS memory cell.
A CMOS memory cell, such as CMOS cell 100, is advantageous to use as a memory cell because it enables zero power operation, zero power operation indicating that the CMOS cell does not continually draw power when the CMOS cell is not changing states.
To assure zero power operation throughout an integrated circuit as well as maximum data retention, cell implants may be utilized in the PMOS transistor 104 and NMOS transistor 104. The cell implants include additional ion implantation to the channel between the source and drain of the PMOS and NMOS transistors 102 and 104 to alter the sum of the magnitude of the threshold of the PMOS and NMOS transistors to be substantially equal to, or greater than Vcc. Then, with Vcc applied to CMOS transistors following the CMOS memory cell, no current leakage will occur in the subsequent CMOS transistors. Further, utilizing cell implants, the magnitude of the thresholds of the PMOS and NMOS transistors may be set so that each is substantially equal to 1/2Vcc so that only a minimal amount of charge needs to be added or removed from the floating gate of a CMOS cell to turn the CMOS cell on or off.
With a CMOS memory cell programmed through the gate oxide of a PMOS transistor 102, as described above, current leakage can occur which can cause a disturb condition wherein electrons are injected onto the common floating gate in a CMOS cell which is not to be programmed. The current leakage during programming can occur because of charge storage in a large n well, such as n well 122 shown in FIG. 2. A large n well is typically shared by a column of cells which all receive the same voltage WC during programming of a particular cell in the column. As shown in Table I, for programming a particular cell, a WL voltage of 5 V is applied. However, for cells in the same column not to be programmed, a WL voltage of 12 V is applied. The 12 V WL voltage is applied to assure that the source of the PMOS transistors, such as 102, of unselected cells are floating, so that if the drains of the PMOS cells of unselected cells are also floating, no leakage current will occur. With no leakage current, deep depletion of the n well will occur, but inversion of the n well will not occur, to cause current leakage in an unselected cell.
However, a large number of cells in an array will require a long Vss line, the long Vss line then having a significant capacitive component, enabling charge storage. By connecting the source of NMOS transistors of unselected cells in a column to the Vss line, a current flow can occur to charge up the capacitance of the Vss line so that drains of NMOS transistors of cells in the column are not floating. With the drain of an NMOS transistor not floating, the drain of a corresponding PMOS transistor to which it is connected will not be floating, but conducting a leakage current. The leakage current occurs when the n well, such as n well 122, is driven from deep depletion to inversion. With such inversion, a disturb condition where electrons are injected onto the floating gate of the unselected cells can occur. Such current leakage during programming is not desirable.